1. Technical Field
The present invention relates generally to integrated circuits, and more particularly, to a latch-up pulse-radiation detector formed using silicon-on-insulator (SOI) technology.
2. Related Art
Silicon-on-insulator (SOI) technology, which is becoming of increasing importance in the field of integrated circuits, deals with the formation of semiconductor devices (e.g., diodes, transistors, etc.) in a relatively thin layer of semiconductor material overlaying a layer of insulating material. SOI technology offers many advantages over bulk complementary metal-oxide-semiconductor (CMOS) processes, including, for example, higher performance, higher packing density, lower power consumption, and a substantial reduction of latch-up.
The cause of latch-up exists in all junction-isolated or bulk CMOS processes: parasitic PNPN paths. The resultant parasitic PNP and NPN bipolar transistors formed by such parasitic PNPN paths, under normal conditions, cannot be activated. However, under some conditions, for example, in response to a spurious current spike, the parasitic PNP or NPN transistors may be activated, forming a circuit with large positive feedback, i.e., latch-up occurs.
Radiation detectors are often formed using bulk CMOS processes to take advantage of latch-up caused by parasitic PNPN bipolar transistors. In particular, bulk CMOS-type radiation detectors are designed to selectively enter a latch-up state in response to an interaction with an alpha particle, a cosmic ray, or other type of radiation that is capable of producing a sufficiently large current spike in the detector. Unfortunately, because one of the characteristics of SOI technology is the substantial reduction of latch-up, it has proven very difficult to produce an SOI radiation detector in which ionizing-radiation-triggered latch-up can occur. Such an SOI-type radiation detector would be desirable because of the many advantages provided by SOI technology over bulk CMOS processes.
A PNPN diode structure, formed using bulk CMOS processes, is commonly employed to produce a radiation detector. Unfortunately, the bulk CMOS structure relies on a current path beneath the device isolation which is absent in SOI technology, thus making this design unsuitable for use as a radiation detector.
The PNPN diode structure 10 shown in FIG. 1 comprises an insulating substrate 12, a silicon layer 14 formed on the insulating substrate 12, a gate oxide layer (e.g., silicon dioxide) 16 formed on the silicon layer 14, a gate layer 18 formed on the gate oxide layer 16, and a silicide strap 20 formed over the gate layer 18. The silicon layer 14 includes a heavily doped P+ region 22, a heavily doped N+ region 24, a lightly-doped N-well 26, and a lightly doped P-well 28. The gate layer 18 includes a heavily doped P+ region 30 and a heavily doped N+ region 32 tied together by the silicide strap 20. The interface 46 between the side 34 of the P+ region 30 and the side 36 of the N+ region 32 of the gate layer 18 is substantially coincident with the interface 48 between the side 38 of the N-well 26 and the side 40 of the P-well 28 of the silicon layer 14. The opposing side 42 of the P+ region 30 of the gate layer 18 extends partially over the P+ region 22 of the silicon layer 14. Similarly, the opposing side 44 of the N+ region 32 of the gate layer 18 extends partially over the N+ region 24 of the silicon layer 14. The PNPN diode structure 10 can be formed using conventional SOI processes known to those skilled in the art.
In operation, as shown in FIG. 2, the P+ region 22 of the silicon layer 14 is tied to a source voltage (e.g., VDD), the N+ region 24 of the silicon layer 14 is tied to ground (e.g., VSS), while the gate layer 18 is at some operational voltage. A parasitic PMOS FET 50 is formed in the silicon layer 14, with its source (Sp) formed by the P+ region 22, its body (Bp) formed by the N-well 26, its drain (Dp) formed by the P-well 28, and its gate (Gp) formed by the P+ region 30 of the gate layer 18. Similarly, a parasitic NMOS FET 52 is formed in the silicon layer 14, with its source (Sn) formed by the N+ region 24, its body (Bn) formed by the P-well 28, its drain (Dn) formed by the N-well 26, and its gate (Gn) formed by the N+ region 32 of the gate layer 18.
The threshold voltage (Vtp) of the parasitic PMOS FET 50 is typically on the order of about −0.2 volts. Therefore, to prevent the parasitic PMOS FET 50 from turning on, the P+ region 30 of the gate layer 18 (i.e., Gp) must be tied to a voltage substantially equal to the source voltage (VDD). Similarly, the threshold voltage (Vtn) of the parasitic NMOS FET 52 is typically on the order of about 0.2 volts. Therefore, to prevent the parasitic NMOS FET 52 from turning on, the N+ region 32 of the gate layer 18 (i.e., Gn) must be tied to a voltage substantially equal to VSS. Therefore, there are two contradictory requirements for the voltage on the gate layer 18: the gate layer 18 must be tied to VDD to prevent the parasitic PMOS FET 50 from turning on, while at the same time, the gate layer 18 must be tied to VSS to prevent the parasitic NMOS FET 52 from turning on. Since these requirements cannot both be met at the same time, one or the other of the parasitic FETs 50, 52, will always turn on in response to a minimal gate bias, and latch-up will be initiated.
Accordingly, there is a need in the art for a radiation detector formed using SOI technology.